The present disclosure relates generally to the field of semiconductor devices, and more particularly, to a method for fabricating a semiconductor device with reduced contact resistance, such as between a contact area silicide and a source/drain substrate.
In semiconductor device fabrication, numerous conductive structures, such as gate electrodes, contacts, vias, and interconnects, may be formed in or above a semiconductor substrate, isolated from one another by dielectric layers. At the various fabrication stages, it may be necessary to form openings in the dielectric layers to allow for contact to underlying regions or layers. Generally, the vertical openings through a dielectric layer that connect the first metal layer to the devices formed in the semiconductor substrate are called “contacts.” The vertical openings in other dielectric layers, such as an opening that connects between an upper metal layer and a lower metal layer, are referred to as “vias.”
A contact opening may expose a doped region such as a source or drain. For example, a contact (plug) connects between a back end of line (BEOL) interconnect and a front end of line (FEOL). Metals like tungsten are often employed for the contact material. Beneath the contact, there are two additional layers between the source or drain and the contact itself. The first layer, a bottom contact barrier, prevents contact materials from diffusing to the source or drain and impacts the leakage. The other layer, between the bottom contact barrier and source or drain, is a layer of silicide, which ensures low parasitic resistance.
High quality contacts are essential to high device yield and reliability, but fabrication of these high quality contacts poses challenges, specifically when trying to maintain a relatively low contact resistance. Ideally, in an ohmic contact interface, a low contact resistance resulting from a difference in work functions does not exist between the silicide and semiconductor substrate. However, in reality, the contact resistance at the silicide/semiconductor substrate interface is relatively high, even though the barrier height between them is low. This often results from implantation processes, which leave implantation induced defects present even after salicidation. The existing defects interact with the silicide, resulting in junction leakage. Other factors also increase the contact resistance, such as the roughness of the silicide/semiconductor interface, work function between silicide and the semiconductor substrate, the substrate doping concentration, etc.
Accordingly, what is needed is a method for improving the contact resistance created in the semiconductor fabrication process.